puts "INFO: Running script [info script]\n"
set CPU_NUM  32

#################################################
# Required variables
# These variables must be correctly filled in for the flow to run properly
#################################################
set DESIGN_NAME "soc_top"


set PWR_NET  "VDD VDDIO"
set GND_NET  "VSS VSSIO"

#set VERSION "V1"
set DESIGN_LIBRARY "dbs/${DESIGN_NAME}"

set STD_LEF_FILE "\
/home/pdk/UMC/UMC110/project/sc/lef/ua11lscll12hdre.lef \
"

set MACRO_LEF_FILE "\
/home/pdk/UMC/UMC110/project/io/lef/ua11gioll33mvire_6m1t40k.lef \
/home/pdk/UMC/UMC110/project/sram/SHTB110_8192X8X4CM16/SHTB110_8192X8X4CM16.lef \
"

set VERILOG_NETLIST_FILES "input/soc_top.mapped.v"
set SDC_FILE "input/soc_top.sdc"


######################################################
# Flow control
######################################################
set FLOW_EFFORT                         "standard" ; # value: express|standard|extreme, default is standard
set TIMING_EFFORT                       "high"     ; # value: low|high, default is high
set CONGESTION_EFFORT                   "auto"     ; # value: low|medium|high|auto, default is auto
set POWER_EFFORT                        "none"     ; # value: none|low|high, default is none

##########################################################
# Variables for init_floorplan
##########################################################
set DIE_BOUNDARY     {{0 0} {2700 0} {2700 1400} {0 1400}}
set PIN_PLACEMENT_FILE   "user_scripts/fp.pin.tcl"
set MACRO_PLACEMENT_FILE  "user_scripts/fp.macro.tcl"


##########################################################
# hold fix
##########################################################
set CLOCK_OPT_FIX_HOLD            1
set ROUTE_OPT_FIX_HOLD            1

##########################################################
# Variables for export
##########################################################
set WRITE_DATA_STEP_NAME               std_filler ; # default use std_filler step, can change to any step
#set WRITE_DATA_TYPE_LIST            "verilog pg_verilog def starrc_def lef tech_lef sdc gds etm"
set WRITE_DATA_TYPE_LIST            "verilog pg_verilog def starrc_def lef tech_lef sdc gds spef"


set MACRO_GDS_FILE     "\
/home/pdk/UMC/UMC110/project/io/gds/ua11gioll33mvire_6m1t40k.gds \
/home/pdk/UMC/UMC110/project/sram/SHTB110_8192X8X4CM16/SHTB110_8192X8X4CM16.gds \
"
#set SUB_BLOCK_GDS_FILE "\
#/home2/users/release/mesh_1_conn_64/final_run4/innovus/mesh_1_conn_64.gds \
#/home2/users/release/block/final_run4/innovus/block.gds \
#"

#control report file for each step
set REPORT_QOR(import)             1
set REPORT_QOR(floorplan)          0
set REPORT_QOR(place)              1
set REPORT_QOR(ccopt)              1
set REPORT_QOR(route)              0
set REPORT_QOR(route_opt)          1
set REPORT_QOR(std_filler)         1







